Threshold Voltage Optimization.
Large minimum-cost flow instances
arising in the linear time-cost tradeoff relaxation of threshold voltage optimization and placement.
T. Brand, D. Faber, S. Held, and P. Mutzel:
A Customized SAT-based Solver for Graph Coloring. arXiv:2504.04821, 2025.
See also our corresponding source code.
S. Held and Y.K.D. Spitzley:
Further Improvements on Approximating the
Uniform Cost-Distance Steiner Tree Problem, Technical Report No. 221263, Research Institute for Discrete Mathematics, University of Bonn, 2022,
arXiv:2211.03830.
G. Posser, E.F.Y. Young, S. Held, Y.-L. Li, D.Z. Pan:
Challenges and Approaches in VLSI Routing
Proc. ISPD, 2022, (preprint),
A. Khazraei and S. Held:
An Improved Approximation Algorithm for the Uniform
Cost-Distance Steiner Tree Problem,
Proc. WAOA 2020, LNCS 12806, pp. 189--203, 2021.
(preprint).
S. Daboul, S. Held, J. Vygen, and S. Wittke:
An approximation algorithm for threshold voltage optimization, ACM Transactions on Design Automation of Electronic Systems 23 (6), Article No. 68, 2018.
(preprint).
S. Held, D. Müller, D. Rotter, R. Scheifele, V. Traub, and J. Vygen:
Global Routing with Timing Constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37(2), 2018, 406--419.
(10.1109/TCAD.2017.2697964),
(preprint).
S. Held and N. Kämmerling:
Two-Level Rectilinear Steiner Trees, Computational Geometry 61, 2017, 48--59
(link,
preprint ,
short version at EUROCG 2015).
S. Held and S.T.Spirkl:
Fast Prefix Adders
for Non-Uniform Input Arrival Times,
Algorithmica 77 (1), 2017, 287--308
(link, preprint).
S. Held and J. Hu:
Gate Sizing, in Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology.
Edited by Luciano Lavagno, Igor L. Markov, Grant Martin, and Louis K. Scheffer, CRC Press, 2016,
245--260 (Chapter 10).
S. Held, D. Müller, Daniel Rotter, Vera Traub and J. Vygen:
Global Routing with Inherent Static Timing Constraints.
Proc. ICCAD 2015, 102--109.
S. Held, S. Hougardy, and J. Vygen:
Chip Design.
in: The Princeton Companion to Applied Mathematics, (N.J.Higham, ed.), Princeton University Press 2015, 804--807.
A. Bock, S. Held, N. Kämmerling, and U. Schorr:
Local Search Algorithms for Timing-Driven Placement under Arbitrary Delay Models.
Proc. 52th DAC, 2015, (preprint).
S. Held and U. Schorr:
Post-Routing Latch Optimization for Timing Closure.
Proc. 51st DAC, 2014.
S. Held and S. T. Spirkl:
A Fast Algorithm for Rectilinear Steiner Trees with Length Restrictions on Obstacles.
Proc. ISPD 2014, pp. 37--44.
S. Held, E. C. Sewell, W. Cook:
Safe Lower Bounds for Graph Coloring. Proc. IPCO 2011, pp. 261--273 .
C. Bartoschek, S. Held, J. Maßberg, D. Rautenbach, J. Vygen:
The repeater tree construction problem.
Information Processing Letters 110 (2010), 1079-1083.
C. Bartoschek, S. Held, D. Rautenbach, J. Vygen:
Fast Buffering for Optimizing Worst Slack and Resource Consumption in Repeater Trees.
Proc. ISPD 2009, pp. 43--50.
C. Bartoschek, S. Held, D. Rautenbach, J. Vygen:
Efficient algorithms for short and fast repeater trees. II. Buffering.
Technical Report No. 07978, Research Institute for Discrete Mathematics, University of Bonn, 2007
C. Bartoschek, S. Held, D. Rautenbach, J. Vygen:
Efficient algorithms for short and fast repeater trees. I. Topology generation.
Technical Report No. 07977, Research Institute for Discrete Mathematics, University of Bonn, 2007
S. Held: Fast Gate Sizing and Timing Closure for Multi-Million Cell Designs.
Technical Report No. 07969, Forschungsinstitut für Diskrete Mathematik, University of Bonn, 2007
C. Bartoschek, S. Held, D. Rautenbach, J. Vygen:
Efficient Generation of Short and Fast Repeater Tree Topologies. Proc. ISPD 2006, pp. 120--127.
S. Held, B. Korte, J. Maßberg, M. Ringe, J. Vygen:
Clock Scheduling and Clocktree Construction for High Performance ASICs. Proc. ICCAD 2003, pp. 232--239.