Thema: VLSI-Design
Termin: montags 14 Uhr c.t. im Seminarraum des Instituts
| Nr. | Datum | Name | Thema | Betreuung |
|---|---|---|---|---|
| 1 | 18.10. / 25.10. | Mitarbeiter | Überblicksvortrag über das VLSI-Design | - |
| 2 | 8.11. | Jennifer Wolf | Zachariasen [2001]:
The Rectilinear Steiner Tree Problem: A Tutorial
In: D.-Z. Du and X. Cheng (eds.): Steiner Trees in Industries, Kluwer Academic Publishers, 2001, 467 - 507 |
Sven Peyer |
| 3 | 15.11. | Rebecca Reiffenhäuser | Vygen [2004]:
Near-Optimum Global Routing with Coupling, Delay Bounds, and Power Consumption
In: G. Nemhauser, D. Bienstock, (eds.): Proceedings of the 10th International IPCO Conference; Springer, Berlin 2004, 308 - 324 |
Dirk Müller |
| 4 | 22.11. | Björn Bales | Hetzel [1998]:
A Sequential Detailed Router for Huge Grid Graphs
Design, Automation and Test in Europe, Proceedings, IEEE 1998, 332 - 338 |
Sven Peyer |
| 5 | 29.11. | Uwe Schuster | Albrecht, Korte, Schietke, Vygen [2002]:
Maximum Mean Weight Cycle in a Digraph and Minimizing Cycle Time of a Logic Chip
Discrete Applied Mathematics 123 (2002), 103 - 127 |
Stephan Held |
| 6 | 6.12. | Monica Wieneke | Chen, Chu, Wong [1999]:
Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation
IEEE Transactions on Computer-Aided Design, vol. 18, no. 7, July 1999, 1014 - 1025 |
Markus Struzyna |
| 7 | 13.12. | Mareike Beutler | Rautenbach, Szegedy, Werber [2003]: The Delay of Circuits whose Inputs have specified Arrival Times | Jürgen Werber |
| 8 | 20.12. | Klaus Dankwart | Rautenbach, Szegedy, Werber [2003]: Delay Optimization of Linear Depth Boolean Circuits with Prescribed Arrival Times | Jürgen Werber |
Scheinkriterien:
erfolgreicher Seminarvortrag, regelmäßige Teilnahme an den Veranstaltungen und aktive MitarbeitProf. Dr. B. Korte,
Prof. Dr. D. Rautenbach,
Prof. Dr. J. Vygen